Selectively performing multi-plane read operations in non-volatile memory
US11048571B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2018 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Apr 1, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method, according to one embodiment, includes: receiving a multi-page read request and predicting whether using a multi-plane read operation to read pages of storage space in memory which correspond to the multi-page read request will result in a bit error rate that is in a predetermined range. In response to predicting that using the multi-plane read operation to read the pages will not result in a bit error rate that is in the predetermined range, a threshold voltage shift (TVS) value is computed for the multi-plane read operation. Furthermore, the pages are read using the multi-plane read operation with the computed TVS. Other systems, methods, and computer program products are described in additional embodiments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.