Storage device and operating method thereof
US11048585B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 12, 2019 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Dec 15, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller includes: a read operation controller for controlling the plurality of memory devices to perform read operation on a plurality of pages included in one stripe; an over-sampling read voltage determiner for determining over-sampling read voltages, based on soft read data of a selected page among at least two pages, when read operations on the at least two pages among the plurality of pages fail; an error bit recovery for recovering error estimation bits included in read data of the selected page, based on an over-sampling read data of the selected page, which is acquired using the over-sampling read voltages; and an error corrector for performing error correction decoding on conversion data obtained by recovering the error estimation bits included in the read data of the selected page. The plurality of pages included in one stripe is included in different memory devices among the plurality of memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.