Patent · US Active

Write assist circuitry for memory

US11049552B1 · kind B1 · utility

4Cited by

5References

20Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Pradeep Raj · Atrauli, IN
Rahul Sahu · Kanchinakote, IN
Sharad Gupta · New Delhi, IN
Chulmin Jung · Boise, US

Key dates

Filing date	Mar 24, 2020
Grant date	Jun 29, 2021
Priority date	—
Expiry date	Mar 24, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/419
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Certain aspects of the present disclosure are directed to a memory circuit. The memory circuit generally includes a memory cell coupled between a bit-line and a complementary bit-line. The memory circuit also includes a first n-type metal-oxide-semiconductor (NMOS) transistor configured to couple the bit-line to a write drive input during a write cycle of the memory circuit. The memory circuit also includes a second NMOS transistor configured to couple the complementary bit-line to a complementary write drive input during the write cycle, and a multiplexer circuit having a first p-type metal-oxide-semiconductor (PMOS) transistor coupled between a voltage rail and the bit-line or the complementary bit-line, the multiplexer circuit being configured to couple, via the first PMOS transistor, the bit-line or the complementary bit-line to the voltage rail during the write cycle.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.