Non-volatile memory with program verify skip
US11049578B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2020 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Feb 19, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Non-volatile memory cells are programmed by applying a programming signal as a series of programming voltage pulses (or other doses of programming) to selected memory cells and verifying the memory cells between programming voltage pulses. To achieve tighter threshold voltage distributions, a coarse/fine programming process is used that includes a two step verification between programming voltage pulses comprising an intermediate verify condition and a final verify condition. Memory cells being programmed that have reached the intermediate verify condition are slowed down for further programming. Memory cells being programmed that have reached the final verify condition are inhibited from further programming. To reduce the number of verify operations performed, a system is proposed for skipping verification at the intermediate verify condition for some programming voltage pulses and skipping verification at the final verify condition for some programming voltage pulses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.