Stacked field-effect transistors having proximity electrodes
US11049890B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2019 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Oct 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Field-effect transistor (FET) devices are described herein that include an insulator layer, a plurality of active field-effect transistors (FETs) formed from an active silicon layer implemented over the insulator layer, a substrate layer implemented under the insulator layer, and proximity electrodes for a plurality of the FETs that are each configured to receive a voltage and to generate an electric field between the proximity electrode and a region generally underneath a corresponding active FET. FET devices can be stacked wherein one or more of the FET devices in the stack includes a proximity electrode. The proximity electrodes can be biased together, biased in groups, and/or biased individually.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.