Semiconductor isolation structures comprising shallow trench and deep trench isolation
US11049932B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2018 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Mar 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to isolation structures for semiconductor devices and, more particularly, to dual trench isolation structures having a deep trench and a shallow trench for electrically isolating integrated circuit (IC) components formed on a semiconductor substrate. The semiconductor isolation structure of the present disclosure includes a semiconductor substrate, a shallow trench isolation (STI) disposed over the semiconductor substrate, a deep trench isolation (DTI) with sidewalls extending from a bottom surface of the STI and terminating in the semiconductor substrate, a multilayer dielectric lining disposed on the sidewalls of the DTI, the multilayer dielectric lining including an etch stop layer positioned between inner and outer dielectric liners, and a filler material disposed within the DTI.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.