Non-volatile memory and manufacturing method for the same
US11049947B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 7, 2019 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Nov 7, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a non-volatile memory and a manufacturing method for the same. A floating gate structure of the non-volatile memory is located on one side of a word line structure, and includes a second gate dielectric layer and a second conductive layer in sequence from bottom to top. The second conductive layer has a first sharp portion, a second sharp portion, and a sharp depression portion located between the two sharp portions. An erasing gate structure is located above the floating gate structure, and includes a tunneling dielectric layer and a third conductive layer in sequence from bottom to top. The tunneling dielectric layer covers tip parts of the first and second sharp portions, and is filled into the sharp depression portion. The third conductive layer has a third sharp portion at a position corresponding to the sharp depression portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.