Synchronous sampling in-phase and quadrature-phase (I/Q) detection circuit
US11050428B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2020 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Sep 2, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2273
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A synchronized I/Q detection circuit is provided. A first subset of input signals and, subsequently, a second subset of input signals are provided by a first multiplexer and received by a first phase detector. Outputs of the first phase detector are receiving, by a first reset and sampling circuit. A second set of input signals are provided by a second multiplexer and received by a second phase detector, from a second multiplexer, while the first multiplexer receives the first and second subsets of input signals. The first subset of input signals has a same phase order as the second set of input signals, and the second subset of input signals has a different phase order than the second set of input signals. Outputs of the second phase detector are received by a second reset and sampling circuit. A comparator outputs a detected phase difference based on the outputs of the first and second reset and sampling circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.