Semiconductor memory device performing command merge operation and operation method thereof
US11055025B2 · kind B2 · utility
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24Claims
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Key dates
| Filing date | Oct 25, 2019 |
| Grant date | Jul 6, 2021 |
| Priority date | — |
| Expiry date | Nov 14, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory device, a Read-Modify-Write (RMW) controller configured to generate a merge command corresponding to at least one command among a read command and a write command which are externally provided, to receive a processing result of the merge command, and to generate a response for the at least one command corresponding to the merge command. The semiconductor memory device further includes a memory controller configured to control the memory device by receiving the merge command and to provide the processing result of the merge command to the RMW controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.