Systems and methods for gate array with partial common inputs
US11055463B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2020 |
| Grant date | Jul 6, 2021 |
| Priority date | — |
| Expiry date | Apr 1, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3953
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and method are provided for automating design of an integrated circuit. In an embodiment, an integrated circuit design file is received that specifies logic elements. A plurality logic elements are identified that share a common input signal. A determination is made that the each of plurality of logic elements include a series of transistors. Upon said determining, the integrated circuit design is modified by identifying first and second transistors for a first of the logic elements, identifying first and second transistors for a second of the logic elements, deleting the second transistor of the second logic element, and routing an output of the first transistor of the second logic element to an input of the second transistor of the first logic element. The modified integrated circuit design is stored in a non-transitory computer-readable medium.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.