Memory device and divided clock correction method thereof
US11056158B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2019 |
| Grant date | Jul 6, 2021 |
| Priority date | — |
| Expiry date | Jan 24, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A memory device includes an internal clock generator, a deserializer, a data comparator, and a clock controller. The internal clock generator generates a plurality of internal clock signals, which have different phases from each other, by dividing a clock signal received from a host. The deserializer deserializes serial test data received from a host as pieces of internal data using the internal clock signals. The data comparator compares reference data with the internal data. The clock controller corrects a clock dividing start time point of the clock signal of the internal clock generator based on the result of the comparison of the reference data and the internal data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.