Semiconductor device and method
US11056400B2 · kind B2 · utility
3Cited by
16References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2019 |
| Grant date | Jul 6, 2021 |
| Priority date | — |
| Expiry date | Oct 11, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0142
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.