One selector one resistor MRAM crosspoint memory array fabrication methods
US11056534B2 · kind B2 · utility
5Cited by
0References
16Claims
0Family size
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Key dates
| Filing date | Jul 2, 2019 |
| Grant date | Jul 6, 2021 |
| Priority date | — |
| Expiry date | Jul 2, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N52/85
Abstract
A memory array is provided that includes a first memory level having a plurality of memory cells each including a corresponding magnetic memory element coupled in series with a corresponding selector element, and a plurality of vias, each of the vias coupled in series with a corresponding one of the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.