Semiconductor device and manufacturing method thereof
US11056580B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 23, 2015 |
| Grant date | Jul 6, 2021 |
| Priority date | — |
| Expiry date | Nov 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device comprise a substrate, source/drain regions, a channel region, a gate dielectric layer and a gate conductive layer, wherein the gate dielectric layer comprises a barrier layer, a storage layer, a first interface layer, a tunneling layer, a second interface layer. In accordance with the semiconductor device and the manufacturing method of the present invention, an interface layer is added between the storage layer and tunneling layer in the gate dielectric by adjusting process step, and the peak concentration and peak location of nitrogen can be flexibly adjusted, effectively improving the quality of the interface between the storage layer and the tunneling layer in the gate dielectric layer, increasing process flexibility, improving device reliability and current characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.