Silicon substrate modification to enable formation of thin, relaxed, germanium-based layer

US11056592B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Karthik Jambunathan · Hillsboro, US
• Cory Bomberger · Portland, US
• Glenn A. Glass · Portland, US
• Anand S. Murthy · Beaverton, US
• Ju H. Nam · Hillsboro, US
• Tahir Ghani · Portland, US

Key dates

• Filing date: Jun 30, 2017
• Grant date: Jul 6, 2021
• Expiry date: Jun 30, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017

Abstract

An integrated circuit (IC) includes a substrate that includes silicon. A first layer is on the substrate and includes a first monocrystalline semiconductor material, the first layer having a plurality of defects. A second layer is on the first layer and includes a second monocrystalline semiconductor material that includes germanium. A strained channel structure is above the first layer. A gate structure is at least above the channel structure. A source region is adjacent the channel structure. A drain region is adjacent the channel structure, such that the channel structure is laterally between the source region and the drain region.