Cory Bomberger
37Patents
2h-index
39Co-inventors
49Inventor score
Filing activity: Jun 30, 2017 → Apr 23, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11222977B2 | Source/drain diffusion barrier for germanium NMOS transistors | Electricity | 8 | Active |
| US11522048B2 | Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs | Electricity | 3 | Active |
| US11532706B2 | Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures | Electricity | 2 | Active |
| US11532734B2 | Gate-all-around integrated circuit structures having germanium nanowire channel structures | Electricity | 2 | Active |
| US11887988B2 | Thin film transistor structures with regrown source and drain | Electricity | 1 | Active |
| US11682731B2 | Fin smoothing and integrated circuit structures resulting therefrom | Electricity | 1 | Active |
| US11990513B2 | Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures | Electricity | 1 | Active |
| US12021149B2 | Fin smoothing and integrated circuit structures resulting therefrom | Electricity | 1 | Active |
| US11164785B2 | Three-dimensional integrated circuits (3DICs) including upper-level transistors with epitaxial source and drain material | Electricity | 1 | Active |
| US11328988B2 | Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication | Electricity | 1 | Active |
| US11735630B2 | Integrated circuit structures with source or drain dopant diffusion blocking layers | Electricity | 0 | Active |
| US11264501B2 | Device, method and system for promoting channel stress in a NMOS transistor | Electricity | 0 | Active |
| US11101356B2 | Doped insulator cap to reduce source/drain diffusion for germanium NMOS transistors | Electricity | 0 | Active |
| US11056592B2 | Silicon substrate modification to enable formation of thin, relaxed, germanium-based layer | Electricity | 0 | Active |
| US11575005B2 | Asymmetrical semiconductor nanowire field-effect transistor | Electricity | 0 | Active |
| US11929320B2 | Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication | Electricity | 0 | Active |
| US11450739B2 | Germanium-rich nanowire transistor with relaxed buffer layer | Electricity | 0 | Active |
| US11189730B2 | Non-selective epitaxial source/drain deposition to reduce dopant diffusion for germanium nMOS transistors | Electricity | 0 | Active |
| US12027585B2 | Source or drain structures with low resistivity | Electricity | 0 | Active |
| US12426342B2 | Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stability | Performing Operations; Transporting | 0 | Active |
| US12237420B2 | Fin smoothing and integrated circuit structures resulting therefrom | Electricity | 0 | Active |
| US11482457B2 | Substrate defect blocking layers for strained channel semiconductor devices | Electricity | 0 | Active |
| US11735670B2 | Non-selective epitaxial source/drain deposition to reduce dopant diffusion for germanium NMOS transistors | Electricity | 0 | Active |
| US11244943B2 | Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material | Electricity | 0 | Active |
| US12027417B2 | Source or drain structures with high germanium concentration capping layer | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.