Vertical memory devices
US11056645B2 · kind B2 · utility
1Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2019 |
| Grant date | Jul 6, 2021 |
| Priority date | — |
| Expiry date | Jul 12, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8836
Abstract
A vertical memory device includes gate electrodes on a substrate and a first structure. The gate electrodes may be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate. The first structure extends through the gate electrodes in the first direction, and includes a channel and a variable resistance structure sequentially stacked in a horizontal direction parallel to the upper surface of the substrate. The variable resistance structure may include quantum dots (QDs) therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.