Snapback electrostatic discharge protection for electronic circuits
US11056880B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2020 |
| Grant date | Jul 6, 2021 |
| Priority date | — |
| Expiry date | Mar 31, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Snapback ESD protection circuits that include an Input/Output pad, a ground source, a first and a second NMOS transistor, and trigger circuit, pad bias circuit, and gate bias circuit. The first transistor drain connects to the pad. The second transistor drain connects to the first transistor source. The second transistor source connects to ground. The trigger circuit connects to the pad and a reference voltage to detect an ESD event at the pad. The pad bias circuit connects to the pad, the trigger circuit, ground, and the reference voltage to manage a voltage level for the reference voltage. The gate bias circuit connects to the reference voltage, a supply voltage, ground, and the gates of the first and second transistor to dynamically control the voltage of each gate of the first and a second NMOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.