Systems and methods for optimizing nested loop instructions in pipeline processing stages within a machine perception and dense algorithm integrated circuit
US11061678B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2020 |
| Grant date | Jul 13, 2021 |
| Priority date | — |
| Expiry date | Dec 18, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method for improving a performance of an integrated circuit includes implementing one or more computing devices executing a compiler program that: (i) evaluates a target instruction set intended for execution by an integrated circuit; (ii) identifies one or more nested loop instructions within the target instruction set based on the evaluation; (iii) evaluates whether a most inner loop body within the one or more nested loop instructions comprises a candidate inner loop body that requires a loop optimization that mitigates an operational penalty to the integrated circuit based on one or more executional properties of the most inner loop instruction; and (iv) implements the loop optimization that modifies the target instruction set to include loop optimization instructions to control, at runtime, an execution and a termination of the most inner loop body thereby mitigating the operational penalty to the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.