Method, apparatus, and system for reducing pipeline stalls due to address translation misses
US11061822B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2018 |
| Grant date | Jul 13, 2021 |
| Priority date | — |
| Expiry date | Oct 31, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus, and system for reducing pipeline stalls due to address translation misses is presented. An apparatus comprises a memory access instruction pipeline, a translation lookaside buffer coupled to the memory access instruction pipeline, and a TLB miss queue coupled to both the TLB and the memory access instruction pipeline. The TLB miss queue is configured to selectively store a first memory access instruction that has been removed from the memory access instruction pipeline as a result of the first memory access instruction missing in the TLB along with information associated with the first memory access instruction. The TLB miss queue is further configured to reintroduce the first memory access instruction to the memory access instruction pipeline associated with a return of an address translation related to the first memory access instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.