Bit-reduced verification for memory arrays
US11062077B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 24, 2019 |
| Grant date | Jul 13, 2021 |
| Priority date | — |
| Expiry date | Jul 15, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Bit-reduction in a verification processes for memory arrays is disclosed. Properties are determined for verification of a circuit that includes a memory array. Circuit data for the circuit is received in a verification environment. When it is determined that the circuit includes a memory array, an address for the memory array is sampled as part of a read operation during verification for the circuit. A determination may be made that the circuit is in compliance with a property of the properties based at least in part on compliance of the read operation with a predetermined model. The sampling of the address replicates a delay expected in physical read operation of the memory array, but with reduced bits communicated or generated per cycle in the verification process because output data is not sampled contrasting the physical read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.