Max Chvalevsky
6Patents
0h-index
10Co-inventors
31Inventor score
Filing activity: Jun 24, 2019 → Mar 30, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US12175178B1 | Fuzzy scoreboard | Physics | 0 | Active |
| US12361195B1 | Extending cover properties in formal verification to generate failure traces that reach end-of-test | Physics | 0 | Active |
| US11062077B1 | Bit-reduced verification for memory arrays | Physics | 0 | Active |
| US12271669B1 | Executing instruction sequences generated from software interactions as part of formal verification of a design under test | Physics | 0 | Active |
| US11768990B1 | Interconnect flow graph for integrated circuit design | Physics | 0 | Active |
| US11544436B1 | Hardware-software interaction testing using formal verification | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.