Digital address compensation for memory devices
US11062761B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2020 |
| Grant date | Jul 13, 2021 |
| Priority date | — |
| Expiry date | Jan 13, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A position of a memory cell to be accessed within a memory field of a memory device is identified. A region associated with the memory field within which the position is located is identified. A compensation parameter comprising a fixed electric step value for the region is identified. The compensation parameter may be selected from a set of compensation parameters or may be calculated based upon the position of the memory cell. The compensation parameter is applied to an action performed on a line connected to the memory cell during the access of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.