Nonvolatile semiconductor memory device which performs improved erase operation
US11062777B2 · kind B2 · utility
3Cited by
8References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 11, 2020 |
| Grant date | Jul 13, 2021 |
| Priority date | — |
| Expiry date | May 11, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in a matrix. The control unit erases data of the memory cells. The control unit interrupts the erase operation of the memory cells and holds an erase condition before the interrupt in accordance with a first command during the erase operation, and resumes the erase operation based on the held erase condition in accordance with a second command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.