Semiconductor package of using insulating frame
US11062990B2 · kind B2 · utility
0Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 28, 2019 |
| Grant date | Jul 13, 2021 |
| Priority date | — |
| Expiry date | Aug 13, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package using an insulating frame of various is disclosed. The insulating frame has a through hole therein, and the semiconductor chip is mounted in the through hole. Further, a via hole is provided in the periphery of the through hole, and a via contact filling the via hole is provided. Whereby the pad of the semiconductor chip is electrically connected to the via contact through the distribution layer. Further, an adhesive buffer layer for increasing the adhesive force is introduced into the upper portion of the insulating frame.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.