Multi-sense circuit for parallel-connected power switches
US11063583B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Dec 19, 2017 |
| Grant date | Jul 13, 2021 |
| Priority date | — |
| Expiry date | Dec 30, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M1/0009
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A multi-sense circuit includes a transistor circuit having sense nodes and a gate node, a peak detector having inputs coupled to the sense nodes of the transistor circuit and an output, and a control circuit having a gate control node coupled to the gate node of the transistor circuit and an overcurrent protection node coupled to the output of the peak detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.