Phase clock correction
US11069397B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2019 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | May 3, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/017
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for phase clock correction are described. The clock correction may, in some examples, include two stages of duty cycle adjustment. In a first stage, the duty cycles of multiple clock signals may be adjusted. These clock signals may be based on an input clock signal and its complement. The duty cycle adjustment provided to a clock signal during this stage may be based on a difference between the duty cycle of the clock signal before adjustment and the duty cycle of another clock signal. In the second stage, the duty cycle of the input clock signal and its complement may be adjusted. The duty cycle adjustment provided to the input clock signal and/or its complement may be based on clock signals generated from the multiple clock signals after their duty cycles have been adjusted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.