Testing multi-port array in integrated circuits
US11069422B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2020 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | Jul 7, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for testing a circuit includes performing, by a test engine, a test of a memory element of the circuit, the test accesses a memory location in the memory element, the memory location is identified by an address, and the memory location is accessed via a first port associated with a first port select bit. The method further includes, in response to detecting a failure associated with the memory location, determining an existing entry for the address in a failed address register, and determining that the existing entry in the failed address register is associated with a second port select bit, distinct from the first port select bit. The method further includes, in response to the second port select bit being distinct from the first port select bit, setting a multi-port failure flag for the memory element that is being tested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.