Memory device with a row repair mechanism and methods for operating the same
US11069426B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2020 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | Feb 20, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, apparatuses and systems related to managing access to a memory device are described. A memory device includes a plurality of banks that each include (1) a plurality of memory cells and (2) a plurality of redundant cells configured to replace one or more target memory cells in the plurality of memory cells. A set of shared fuses and latches may be used to store a row address for each repair that may be implemented in one of the plurality of banks. A shared match circuit coupled to the set of shared latches and the plurality of memory banks may be configured to at least partially implement a row repair for the row address for a bank associated with a commanded operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.