Semiconductor structure and method of forming same
US11069559B1 · kind B1 · utility
2Cited by
1References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2020 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | Jun 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76264
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure and method for forming such a structure are disclosed by the present invention. In the method, before a first trench in a pre-processed substrate is filled with any filling material, an auxiliary layer is formed over an inner surface of the first trench. Afterward, a first filling dielectric is formed and an etch back process is performed so that a top surface of the first filling dielectric is higher than that of the pre-processed substrate, and a second filling dielectric is then formed and subject to a second planarization process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.