Method of forming multi-threshold voltage devices using dipole-high dielectric constant combinations and devices so formed
US11069576B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 29, 2020 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | Jul 29, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method provides a gate structure for a plurality of components of a semiconductor device. The method provides a first dipole combination on a first portion of the components. The first dipole combination includes a first dipole layer and a first high dielectric constant layer on the first dipole layer. A second dipole combination is provided on a second portion of the components. The second dipole combination includes a second dipole layer and a second high dielectric constant layer on the second dipole layer. The first dipole combination is different from the second dipole combination. At least one work function metal layer is provided on the first dipole combination and the second dipole combination. A low temperature anneal is performed after the step of providing the work function metal layer(s). A contact metal layer is formed on the work function metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.