Inventor · Austin, TX, US

Wei-E Wang

30Patents
8h-index
21Co-inventors
71Inventor score

Filing activity: Sep 15, 2009 → Aug 6, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US9064699B2 Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods Electricity 29 Active
US9812449B2 Multi-VT gate stack for III-V nanosheet devices with reduced parasitic capacitance Electricity 29 Active
US9941405B2 Nanosheet and nanowire devices having source/drain stressors and methods of manufacturing the same Electricity 23 Active
US10026652B2 Horizontal nanosheet FETs and method of manufacturing the same Electricity 19 Active
US9905672B2 Method of forming internal dielectric spacers for horizontal nanosheet FET architectures Electricity 11 Active
US9793403B2 Multi-layer fin field effect transistor devices and methods of forming the same Electricity 9 Active
US8524562B2 Method for reducing Fermi-Level-Pinning in a non-silicon channel MOS device Electricity 8 Active
US9343303B2 Methods of forming low-defect strain-relaxed layers on lattice-mismatched substrates and related semiconductor structures and devices Electricity 8 Active
US9773906B2 Relaxed semiconductor layers with reduced defects and methods of forming the same Electricity 6 Active
US10770353B2 Method of forming multi-threshold voltage devices using dipole-high dielectric constant combinations and devices so formed Electricity 4 Active
US10586738B2 Method of providing source and drain doping for CMOS architecture including FinFET and semiconductor devices so formed Electricity 3 Active
US9218964B2 Antiphase domain boundary-free III-V compound semiconductor material on semiconductor substrate and method for manufacturing thereof Electricity 2 Active
US9870940B2 Methods of forming nanosheets on lattice mismatched substrates Electricity 2 Active
US11088258B2 Method of forming multiple-Vt FETs for CMOS circuit applications Electricity 1 Active
US10026751B2 Semiconductor device including a repeater/buffer at higher metal routing layers and methods of manufacturing the same Electricity 1 Active
US10446400B2 Method of forming multi-threshold voltage devices and devices so formed Electricity 1 Active
US11476121B2 Method of forming multi-threshold voltage devices and devices so formed Electricity 1 Active
US10727297B2 Complimentary metal-oxide-semiconductor circuit having transistors with different threshold voltages and method of manufacturing the same Electricity 1 Active
US11605574B2 Method of forming a thermal shield in a monolithic 3-d integrated circuit Electricity 0 Active
US11189600B2 Method of forming sacrificial self-aligned features for assisting die-to-die and die-to-wafer direct bonding Electricity 0 Active
US11081590B2 Metal oxide semiconductor field effect transistor with crystalline oxide layer on a III-V material Electricity 0 Active
US9698234B2 Interface layer for gate stack using O3 post treatment Electricity 0 Active
US10475930B2 Method of forming crystalline oxides on III-V materials Electricity 0 Active
US10971420B2 Method of forming a thermal shield in a monolithic 3-D integrated circuit Electricity 0 Active
US11069576B2 Method of forming multi-threshold voltage devices using dipole-high dielectric constant combinations and devices so formed Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.