Semiconductor device and method
US11069579B2 · kind B2 · utility
4Cited by
14References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2019 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | Jun 3, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a device includes: a first fin extending from a substrate; a gate stack disposed on the first fin; a source/drain region disposed in the first fin; a contact etch stop layer (CESL) disposed over the source/drain region; a gate spacer extending along a side of the gate stack; and a dielectric plug disposed between the CESL and the gate spacer, where the dielectric plug, the CESL, the gate spacer, and the source/drain region collectively define a void physically separating the gate stack from the source/drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.