Shiang-Bau Wang
79Patents
8h-index
65Co-inventors
81Inventor score
Filing activity: Nov 4, 1999 → May 15, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6201208A | Method and apparatus for plasma processing with control of ion energy distribution at the substrates | Electricity | 120 | Expired |
| US6586886B1 | Gas distribution plate electrode for a plasma reactor | Electricity | 68 | Expired |
| US7947551B1 | Method of forming a shallow trench isolation structure | Electricity | 28 | Active |
| US8609497B2 | Method of dual EPI process for semiconductor device | Electricity | 26 | Active |
| US6652712B2 | Inductive antenna for a plasma reactor producing reduced fluorine dissociation | Electricity | 25 | Expired |
| US6667577B2 | Plasma reactor with spoke antenna having a VHF mode with the spokes in phase | Electricity | 17 | Expired |
| US8071481B2 | Method for forming highly strained source/drain trenches | Electricity | 11 | Active |
| US6677712B2 | Gas distribution plate electrode for a plasma receptor | Electricity | 11 | Expired |
| US8093146B2 | Method of fabricating gate electrode using a hard mask with spacers | Electricity | 8 | Active |
| US8598675B2 | Isolation structure profile for gap filling | Electricity | 8 | Active |
| US7301645B2 | In-situ critical dimension measurement | Electricity | 8 | Expired |
| US8598661B2 | Epitaxial process for forming semiconductor devices | Electricity | 7 | Active |
| US8193094B2 | Post CMP planarization by cluster ION beam etch | Electricity | 7 | Active |
| US10269787B2 | Metal gate structure cutting process | Electricity | 7 | Active |
| US9218974B2 | Sidewall free CESL for enlarging ILD gap-fill window | Emerging Cross-Sectional Technologies | 6 | Active |
| US8372755B2 | Multilayer hard mask | Electricity | 6 | Active |
| US7732878B2 | MOS devices with continuous contact etch stop layer | Electricity | 6 | Active |
| US8383485B2 | Epitaxial process for forming semiconductor devices | Electricity | 6 | Active |
| US9613959B2 | Method of forming metal gate to mitigate antenna defect | Electricity | 6 | Active |
| US8461015B2 | STI structure and method of forming bottom void in same | Electricity | 5 | Active |
| US8900957B2 | Method of dual epi process for semiconductor device | Electricity | 5 | Active |
| US10304178B2 | Method and system for diagnosing a semiconductor wafer | Physics | 5 | Active |
| US8361338B2 | Hard mask removal method | Electricity | 5 | Active |
| US8822304B2 | Isolation structure profile for gap filing | Electricity | 4 | Active |
| US11069579B2 | Semiconductor device and method | Electricity | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.