Wafer-level fan-out package with enhanced performance
US11069590B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2019 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | Jun 27, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a wafer-level fan-out package that includes a first thinned die, a second die, a multilayer redistribution structure underneath the first thinned die and the second die, a first mold compound over the second die, a second mold compound over the multilayer redistribution structure, and around the first thinned die and the second die, and a third mold compound. The second mold compound extends beyond the first thinned die to define an opening within the second mold compound and over the first thinned die, such that a top surface of the first thinned die is at a bottom of the opening. A top surface of the first mold compound and a top surface of the second mold compound are coplanar. The third mold compound fills the opening and is in contact with the top surface of the first thinned die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.