Dielectric barrier at non-volatile memory tile edge

US11069855B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Kevin Lee Baker · Boise, US
• Robert K. Grubbs · Boise, US
• Farrell M. Good · Meridian, US
• Ervin T. Hill · Boise, US
• Bhumika Chhabra · Boise, US
• Jay Steven Brown · Boise, US

Key dates

• Filing date: Jul 1, 2019
• Grant date: Jul 20, 2021
• Expiry date: Jul 1, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/063

Abstract

An oxidation barrier for non-volatile memory with materials sensitive to temperature and/or cross contamination (e.g., chalcogenide materials) are described The barrier can be formed, for example, around the boundaries of a non-volatile memory tile (also known as a block or sub-array). For example, a non-volatile memory device can include an oxidation barrier on a side wall of a trench between adjacent memory tiles.