Circuit testing system and circuit testing method
US11073555B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2019 |
| Grant date | Jul 27, 2021 |
| Priority date | — |
| Expiry date | Dec 29, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31716
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present disclosure relates to a circuit testing system, including a control circuit and an I/O interface circuit. The control circuit is electrically connected to a test machine, and is configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to propagate a scan test signal sended from the test machine to the scan chain circuit. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to propagate a response signal generated by the circuit under test to the test machine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.