Compute optimizations for neural networks using bipolar binary weight
US11074072B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2019 |
| Grant date | Jul 27, 2021 |
| Priority date | — |
| Expiry date | Jan 9, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment provides for a compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a bipolar binary weight associated with a neural network and an arithmetic logic unit including a multiplier, an adder, and an accumulator register. To execute the decoded instruction, the multiplier is to perform a multiplication operation on the multi-bit input based on the bipolar binary weight to generate an intermediate product and the adder is to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.