Responder signal circuitry for memory arrays finding at least one cell with a predefined value
US11074973B2 · kind B2 · utility
3Cited by
11References
3Claims
0Family size
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Key dates
| Filing date | Dec 13, 2017 |
| Grant date | Jul 27, 2021 |
| Priority date | — |
| Expiry date | Dec 13, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/046
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory array of non-volatile memory cells arranged in rows and columns and responder signal circuitry. The responder signal circuitry performs a calculation on a row of the memory array and generates a responder signal indicating that there is at least one cell in the row having a predefined value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.