Insulated gate power semiconductor device and method for manufacturing such a device
US11075285B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2018 |
| Grant date | Jul 27, 2021 |
| Priority date | — |
| Expiry date | Oct 11, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/266
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An insulated gate power semiconductor device includes an (n-) doped drift layer between an emitter side and a collector side. A p doped protection pillow covers a trench bottom of a trench gate electrode. An n doped enhancement layer having a maximum enhancement layer doping concentration in an enhancement layer depth separates the base layer from the drift layer. An n doped plasma enhancement layer having a maximum plasma enhancement layer doping concentration covers an edge region between the protection pillow and the trench gate electrode. The N doping concentration decreases from the maximum enhancement layer doping concentration towards the plasma enhancement layer and the N doping concentration decreases from the maximum plasma enhancement layer doping concentration towards the enhancement layer such that the N doping concentration has a local doping concentration minimum between the enhancement layer and the plasma enhancement layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.