Techniques for MRAM MTJ top electrode connection
US11075335B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2019 |
| Grant date | Jul 27, 2021 |
| Priority date | — |
| Expiry date | May 10, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01F10/3254
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments relate to a method for manufacturing a memory device. The method includes forming a first masking layer disposed over a dielectric layer, the first masking layer exhibiting sidewalls defining an opening disposed above a magnetoresistive random-access memory (MRAM) cell located in an embedded memory region. A first etch is performed to form a first via opening within the dielectric layer above the MRAM cell. A top electrode via layer formed over the MRAM cell and the dielectric layer. A first planarization process performed on the top electrode via layer to remove part of the top electrode via layer and define a top electrode via having a substantially flat top surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.