Logic built-in self test dynamic weight selection method
US11079433B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2019 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | Nov 25, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3187
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An approach for testing, including a self-test method, a semiconductor chip is disclosed. The approach generates test patterns, including weighted random test patterns, for testing random pattern resistant faults, and un-modeled faults directed at specific logic groups, where the dynamically generated test pattern weights are configured to optimize test coverage and test time. The dynamically generated test patterns are based on factors related to random pattern resistant logic structures interconnected via scan chains. More particularly, the dynamically generated test patterns are designed to enable fault detection within logic structures that are resistant to fault detection when tested with random patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.