Address manipulation using indices and tags
US11080062B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2020 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | Jan 31, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30058
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N−1), and the branch history in table T(N−1) is of greater length than the branch history of table T(N−2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.