Method to ensure forward progress of a processor in the presence of persistent external cache/TLB maintenance requests
US11080188B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2018 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | Dec 25, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for efficiently handling maintenance requests among multiple processors. In various embodiments, a given processor of multiple processors receives a maintenance request. If maintenance requests are not currently being blocked, then the given processor determines a type of the maintenance request and updates one or more maintenance type counters based on the type. If one or more counters exceed a threshold, an indication is generated specifying maintenance requests received at a later time are to be held. The received maintenance request is processed. Different types of maintenance requests are used for invalidating entries in the instruction cache, for invalidating entries in a TLB and for synchronizing page table updates. Afterward, software applications continue processing. Forward progress of the software applications is measured using one or more metrics. If forward progress has been achieved, then one or more maintenance type counters are reset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.