Memory cell arrangement and methods thereof

US11081159B1 · kind B1 · utility

Assignee

• Ferroelectric Memory GmbH · DE

Inventors

• Rolf Jähne · Dresden, DE
• Marko Noack · Dresden, DE

Key dates

• Filing date: Jul 15, 2020
• Grant date: Aug 3, 2021
• Expiry date: Jul 15, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/121
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory cell arrangement is provided that may include: a read-out circuit and a memory cell including: a first terminal, a second terminal, and a third terminal; the memory cell may be configured to control current flow between the second terminal and the first terminal as a function of a first voltage present at the first terminal, a third voltage applied at the third terminal, and a memory state of the memory cell. The read-out circuit is configured to: generate a characteristic voltage at the bitline by applying the third voltage at the third terminal and a second voltage at the second terminal, the characteristic voltage representing the memory state of the memory cell, and to determine the memory state of the memory cell based on sensing the characteristic voltage.