Mixed digital-analog memory devices and circuits for secure storage and computing
US11081168B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2020 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | May 18, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device includes a plurality of memory cells arranged in a matrix, a plurality of word lines extended in a row direction, and a plurality of bit lines extended in a column direction. Each of the memory cells is coupled to one of the word lines and one of the bit lines. The memory device further includes a word-line control circuit coupled to and configured to control the word lines, a first bit-line control circuit configured to control the bit lines and sense the memory cells in a digital mode, and a second bit-line control circuit configured to bias the bit lines and sense the memory cells in an analog mode. The first bit-line control circuit is coupled to a first end of each of the bit lines. The second bit-line control circuit is coupled to a second end of each of the bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.