Erase suspend scheme in a storage device
US11081187B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2019 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | Feb 13, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operating a storage device, including; performing, by a non-volatile memory, an erase operation on a block of memory in the non-volatile memory, where the non-volatile memory is coupled to a controller; receiving, by the non-volatile memory, a host-transaction within a first time period, where, the non-volatile memory is coupled to a host device; and suspending, by the non-volatile memory, an erase operation in response to receiving the host-transaction by: determining the erase operation has completed a charge phase; and suspending the erase operation during a pulse phase of the erase operation. The method additionally includes the non-volatile memory maintaining a loop counter and a pulse counter, where: the loop counter increments in response to completion of an erase loop, and the pulse counter increments in response to completion of an erase pulse, where the erase pulse is applied during a pulse phase of the erase operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.