Failing address registers for built-in self tests
US11081202B2 · kind B2 · utility
1Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2019 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | Oct 18, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method includes receiving a memory address of a memory location in a memory that has been identified to be failing. The method further includes determining that the memory location is from a particular portion of the memory. The method further includes, in response to a number of memory locations that are identified to be failing from the particular portion of the memory being below a predetermined threshold, logging the memory address in a set of failing address registers associated with the memory, otherwise, skipping the logging of the memory address in the failing address registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.