Method for manufacturing electronic package
US11081415B2 · kind B2 · utility
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8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2020 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | Apr 29, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.