Three-dimensional memory devices and fabrication methods thereof
US11081496B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 14, 2019 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | Aug 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
Abstract
Embodiments of a method for forming three-dimensional (3D) memory devices include the following operations. First, an initial channel hole is formed in a stack structure of a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset is formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel is further formed by filling the channel hole with a channel-forming structure. The semiconductor channel may have a memory layer having a first memory portion surrounding a bottom of each second layer and a second memory portion connecting adjacent first memory portions. The first memory portion and the second memory portion may be staggered along a vertical direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.